Savvychip Technologies

ASIC Design Verification Engineers

  • 07 November, 2017
  • 3 - 6 years
  • Hyderabad, Bengaluru/Bangalore
  • Not disclosed


  • Verilog
  • System Verilog
  • UVM
  • Digital
  • DDR
  • AXI
  • AHB
  • USB
  • PCIe
  • HDMI
  • C++
  • Perl/Python/TCL

Job Description

1. Strong in digital design fundamentals.
2. Hands on experience in Verilog, System Verilog, C++.
3. Hands on Experience in using Verification Methodologies like VMM, OVM, UVM.
4. Desirable experience: Any of the following protocols: preferred DDR, AXI, AHB, ETHERNET, USB, HDMI, and PCIe.
5. Hands on experience in developing test plan and Coverage plan for IP’s in ASIC.
6. Hands on experience in developing test bench include test bench components, Functional/Code/Netlist coverage model, and Test cases and verify the functionality of complex IP blocks in ASIC.
7. Very good understanding of system level architecture and validation flows.
8. Good hands-on expertise in scripting languages Perl/Python/TCL.

Interested Professionals with minimum of 3 years of experience can apply.

Company Profile

Savvychip Technologies is a provider of IT and ITES lofty ending and strategic in process and proof aid providers to emerging technologies of Semiconductor, Embedded systems and Telecom.

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